1. Field of the invention
The present invention relates generally to integrated circuit carriers and in particular to plastic ball grid array carriers and chip-scale-packaging that is relatively insensitive to delamination when subjected to a moisture sensitivity test commonly referred to as a xe2x80x9cpopcorn testxe2x80x9d.
2. Description of Related Art
In a conventional plastic ball grid array (PBGA) package a silicon die is mounted on a die pad of a multilayer organic substrate. The entire die pad area of the substrate is coated with an adhesive which bonds the silicon die to the substrate.
Fractures created in the adhesive material, or delamination at the adhesive-substrate interface are the most common causes of PBGA package failure. Such a failure is very common in the xe2x80x9cpopcornxe2x80x9d test which is a moisture sensitivity test. Conventional PBGA packages can only pass the Institute for Interconnecting and Packaging Electronic Circuits (IPC) and the Joint Election Device Engineering Council (JEDEC) Level 3 Moisture Sensitivity Test. Some advanced PBGA packages can pass the Level 2 Moisture Sensitivity Test, but the Level 1 Moisture Sensitivity Test remains extremely challenging.
The IPC/JEDEC Moisture Sensitivity Test (the popcorn test) has 3 levels. Level 3 Moisture Sensitivity requires that the PBGA package be subjected to 30xc2x0 C. at 60% relative humidity for 192 hours, then cycled through three IR/convection heating cycles which follow specific requirements. Level 2 Moisture Sensitivity requires that the PBGA package be subjected to 85xc2x0 C. at 60% relative humidity for 168 hours and then cycled through three IR/convection heating cycles. Level 1, which is the highest level of moisture insensitivity, requires that the PBGA package be subjected to 85xc2x0 C. at 85% relative humidity for 168 hours, then subjected to three cycles of IR/convection heating (See JEDEC document No. JESD22-A112-A Moisture-Induced Stress Sensitivity for Plastic Surface Mount Devices).
Moisture inside a plastic PBGA package turns to steam and expands rapidly when the package is exposed to the high temperatures of VPR (vapor phase reflow), IR (infrared) soldering, or, if the package is submerged in molten solder, wave soldering. Under certain conditions, the pressure from the expanding moisture and steam can cause internal delamination of the plastic from the chip and/or substrate, internal cracks that do not extend to the outside of the package, band damage, wire necking, bond lifting, thin film cracking, or cratering beneath the bonds. In the most severe case, the stress can result in external package cracks. This is commonly referred to as the xe2x80x9cpopcornxe2x80x9d phenomenon because the internal stress causes the package to bulge and then crack with an audible xe2x80x9cpopxe2x80x9d sound. Surface mount devices (SMD) such as PBGA packages are more susceptible to this problem than through-hole parts because they are exposed to higher temperatures during reflow soldering. The reason for this is that the soldering operation must occur on the same side of the circuit board as the surface mount device. For through-hole devices, the soldering operation occurs under the circuit board, which shields the through-hole devices from the hot solder. Also generally, SMDs have a smaller minimum plastic thickness from the chip or mount pad interface to the outside of the plastic package.
Various techniques have been used to either limit the amount of humidity a PBGA package is subjected to between manufacturing of the package and the time of soldering to a printed circuit card. Techniques have also been used to help the PBGA package to pass higher levels of the popcorn test.
To limit the amount of moisture a PBGA package is subjected to prior to soldering to a printed circuit board, PBGA packages are packed and shipped in hermetic bags to prevent the absorption of moisture from the environment. For PBGA packages that are not packed in hermetic bags or that have been subjected to the environment for sometime, it is an industry standard to bake dry the packages before surface mounting. The additional steps of either placing the PBGA packages in hermetic bags, or baking them increases the manufacturing cost of a device or a product.
Another technique that has been used to increase a PBGA package""s resistance to a popcorn failure has been to increase the adhesion strength between the PBGA substrate and the die. One approach has been to formulate encapsulating materials and die-attachment materials with high adhesion strength. Still yet another technique for further increasing adhesion between, for example, the substrate and the encapsulating material is to clean the PBGA package with a plasma process before encapsulation, or to chemically modify the substrate surface via graft co-polymerization. These techniques, which do increase adhesion, all require extra steps and generally add additional production costs.
Another technique that has been used to prevent popcorn package cracking is to incorporate minute through-holes in the substrate in the area directly below the die-attach adhesive material and the chip. The through-holes provide a path for some of the vaporizing moisture to escape at solder flow temperatures thereby avoiding a pressure build-up and potential popcorn cracking. A drawback with this technique is that the die may not be completely sealed from environmental elements and contaminants.
What is needed is a low or no-additional-cost method and structure for providing a plastic BGA package that can meet the IPC/JEDEC Level 1 Moisture Sensitivity Test. An ideal structure or method should not add cost-increasing steps or cost-increasing materials to the manufacture of PBGA packages or assembly of PBGA packages onto a circuit board.
The present exemplary embodiments of the present invention provide a plastic ball grid array (PBGA) package that can pass the IPC, EIA/JEDEC Level 1 Moisture Sensitivity Test, commonly referred to as the xe2x80x9cpopcorn testxe2x80x9d by providing a PBGA package that incorporates one or more design features which (1) maximize the strong interfacial contact between encapsulant (mold compound, glob top, etc.) and the laminate core (BT, FR4, etc.); (2) minimize the weak interfacial contact between encapsulant (mold compound, glob top, etc.) and metal (gold-plated copper); and (3) extend the solder mask material to overlap both the metal and laminate core at the metal/laminate core interface.